Maintaining a reputation for quality and reliability, Comtech EF Data is recognized as a technology leader and innovator. Below are examples of our advanced technologies that optimize satellite communications. |
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DoubleTalk® Carrier-in-Carrier®
Our revolutionary and award-winning DoubleTalk Carrier-in-Carrier is based on Applied Signal Technology’s patented “Adaptive Cancellation” technology that allows full duplex satellite links to transmit concurrently in the same segment of transponder bandwidth. When combined with our advanced forward error correction and modulation techniques, DoubleTalk Carrier-in-Carrier delivers improved satellite transponder utilization and unprecedented operating expense savings.
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Low Density Parity Check (LDPC) Coding & 8-QAM Modulation
When used in networks with lower FEC coding rates and higher data rates, the power and bandwidth savings offered by LDPC are most apparent. In conjunction with LDPC is 8-QAM modulation, which exhibits far superior performance compared with conventional 8-PSK. When LDPC and 8-QAM are combined, satellite transponder utilization can be maximized, resulting in minimized operating expenses. |
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2nd Generation Turbo Product Coding (TPC)
Offers increased coding gain, lower decoding delay, and significant bandwidth savings when compared to traditional methods. The range of code rates offered spans Rate 5/16 through 0.95, depending on modulation type.
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Dynamic Single Carrier per Channel (dSCPC)
The Vipersat Management System (VMS) is the engine that provides dynamic SCPC bandwidth management of space segment. When a node in the network has an application to transport over the satellite link, dSCPC technology provides the mechanism to automatically establish the SCPC carrier for that transmission. dSCPCresizes the carrier based on the increase or decrease in applications being sent over the link, and returns the remote to its home state once the application is completed. |
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Data Rates Up to 155 Mbps
Select Comtech EF Data satellite modems support data rates up to 155 Mbps. Key to supporting a range of high data rate applications (broadcast, circuit restoral, military) the modems provide exceptional power and bandwidth efficiency. |
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Daisy Chain Redundancy Switching
Our up and down converters utilize the patented “Daisy Chain” integrated switching technology. The Daisy Chain design removes the relays associated with a centralized protection switch tray and distributes them across the individual converters. CEFD was awarded patent 5,666,646 on this distributed protection switch topology. Daisy Chain technology successfully eliminates a central switching chassis, two power supplies, a microprocessor, and several long, costly cables. Widely accepted in the industry, CEFD's Daisy Chain provides both pricing and marketing advantages. |
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Demonstrating technology leadership and innovation, Comtech EF Data holds a number of patents. For details on the patents that Comtech EF Data holds, please visit the United States Patent and Trademark Office web site. |
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Method & System for Modulating and Detecting High Data Rate Symbol Communications
Patent Number 7,254,188
A method and system for modulating and detecting high data rate symbol communications provides superior performance in channels having a fixed spectral efficiency. A quadrature amplitude modulation (QAM) constellation and an optimized mapping are employed to encode/detect a communications signal and error correction is provided using high speed forward error correction techniques. A log likelihood detection scheme and/or a novel phase detector may be employed to further enhance performance. |
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Digital IF processing block having finite impulse response (FIR) decimation stages
Patent Number 7,213,042
A digital Intermediate Frequency (IF) processing block including a decimation filter having Finite Impulse Response (FIR) decimation stages provides improved performance over a Hogenauer decimating filter. The filter comprises multiple integrator stages followed by multiple FIR decimating stages. The zeros of the filter are tunable by adjusting the integer coefficients of the FIR stages providing tunability of the cut-off response, as opposed to the fixed sinc response of the Hogenauer filter. As a result, the number of required stages for a particular steepness is reduced, dramatically reducing the amount of digital circuitry required to implement a particular filter design. The improved filter is especially suitable for use in digital IF stages in receivers, and for code-based applications where selectable decimation rate is desired and a fast multiply is not available. |
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Digital decimation filter having finite impulse response (FIR) decimation stages
Patent Number 7,117,235
A digital decimation filter having Finite Impulse Response (FIR) decimation stages provides improved performance over a Hogenauer decimating filter. The filter comprises multiple integrator stages followed by multiple FIR decimating stages. The zeros of the filter are tunable by adjusting the integer coefficients of the FIR stages providing tunability of the cut-off response, as opposed to the fixed sinc response of the Hogenauer filter. As a result, the number of required stages for a particular steepness is reduced, dramatically reducing the amount of digital circuitry required to implement a particular filter design. The improved filter is especially suitable for use in digital intermediate frequency (IF) stages in receivers, and for code-based applications where selectable decimation rate is desired and a fast multiply is not available. |
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Method and apparatus for selectively accelerating network communications
Patent Number 6,937,560
A method and apparatus for selectively accelerating network communications provides improved operation of network communications through channels with long delays, such as a satellite communications channel. A configuration management mechanism provides a selection of acceleration configuration for particular addresses of devices that may communicate through the communications channels. Acceleration may be bypassed for particular addresses or classes of devices within the network and priorities may be assigned, permitting a cut-off of acceleration when a threshold number of sessions is reached. The method and system may also allow a higher priority class of session to preempt lower priority session by removing resources from the lower priority session and assigning them to the higher priority session. The data rate of the lower priority session is then lowered (due to the absence of acceleration or reduced buffer size) to reduce traffic flow. |
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Digital summing phase-lock loop circuit with sideband control and method therefor
Patent Number 6,753,711 B2
A digital summing phase-lock loop circuit with sideband control provides high accuracy and high speed acquisition in a multi-loop frequency synthesizer. A digital phase comparator is used to control a voltage-controlled oscillator in response to inputs from multiple external loops. An initial sweep condition is set by a sweep control circuit to provide resolution of lock ambiguities in the multiple external loops. Sideband selection may be performed by selecting on of an inverted or non-inverted output of the digital phase comparator. |
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Hybrid analog-digital phase lock loop multi-frequency synthesizer
Patent Number 6,028,460
A hybrid multi-frequency synthesizer is comprised of an analog phase lock loop, a digital phase lock loop and a phase lock loop monitor. The digital phase lock loop provides an accelerated, accurate frequency acquisition mode for the synthesizer. The analog phase lock loop provides a robust operating mode after frequency acquisition is achieved. The phase lock loop monitor provides a control circuit that monitors the synthesizer for frequency and phase perturbations. The phase lock loop monitor controls an electronic switch that selects either the analog or digital phase lock loop. The invention is further characterized by programmable band pass filtering, peak sensitivity detection and a fast lock feature. |
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Radio frequency (RF) converter system with distributed protection switching and method therefor
Patent Number 5,666,646
The present invention relates to an improved RF converting system. The RF converting system is comprised of a plurality of RF converter modules which are configured for redundant system operation using distributed protection switching in an active "daisy chain" configuration. The "daisy chain" configuration distributes the converter protection switching functions to each individual RF converter module through a switching module coupled to each of the RF converter modules. The "daisy chain" terminates in a backup RF converter which assumes the frequency and attenuation of a faulted RF converter module. A high speed bus provides communication interface between each of the online RF converter modules and the backup RF converter module so that the backup RF converter module can detect faults and reconfigure the system to replace a failed RF converter module. When a fault is detected on an RF converter module, the faulted RF converter module can be detached from the active RF converting system by separating the RF converter module from its switch module leaving the active online RF converting system intact through the switch module. The distributed protection switching in an active "daisy chain" configuration may also be used to provide reliable backup protection for other types of communication equipment. |
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Advanced Technologies & Patents